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general description the ds3992 is a low-cost, two-channel controller for cold-cathode fluorescent lamps (ccfls) that are used to backlight liquid crystal displays (lcds). the ds3992 can drive multiple ccfls per channel, making it ideal for 4- and 6-lamp lcd pc monitor and tv applications. the ds3992 uses a push-pull drive scheme to convert a dc voltage (5v to 24v) to the high voltage (300v rms to 1400v rms ) ac waveform that is required to power the ccfls. the push-pull drive scheme uses a minimal number of external components, which reduces compo- nent and assembly cost and makes the printed circuit board (pc board) design easy to implement. the push- pull drive scheme also provides an efficient dc-to-ac conversion and produces near-sinusoidal waveforms. applications lcd pc monitors lcd-tvs features two-channel ccfl controller for backlighting lcd panels for pc monitors and lcd-tvs minimal bom provides low-cost inverter solution per-channel lamp fault monitoring for lamp- open, lamp overcurrent, failure to strike, and overvoltage conditions accurate (?0%) on-board oscillator for lamp frequency (40khz to 80khz) accurate (?0%) on-board oscillator for dpwm burst-dimming frequency (90hz to 220hz or 180hz to 440hz) device supply undervoltage lockout inverter supply undervoltage lockout burst-dimming soft-start minimizes audible transformer noise strike frequency boost 100% to < 10% dimming range 4.5v to 5.5v single-supply operation -40? to +85? temperature range 16-pin so package (150 mils) ds3992 two-channel, push-pull ccfl controller ______________________________________________ maxim integrated products 1 1 2 so-150 top view 3 4 5 6 7 8 14 13 16 15 12 11 10 9 ovd2 lcm1 ovd1 ga2 v cc v cc ga1 gb1 posc losc gb2 v cc gnd svm bright lcm2 ds3992 pin configuration rev 0; 9/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes lead-free package. t&r denotes tape-and-reel package. ordering information part temp range dimming frequency range bright polarity pin-package ds3992z-09p+ -40? to +85? 90hz to 220hz positive 16 so-16 (150 mils) ds3992z-09n+ -40? to +85? 90hz to 220hz negative 16 so-16 (150 mils) DS3992Z-18P+ -40? to +85? 180hz to 440hz positive 16 so-16 (150 mils) ds3992z-18n+ -40? to +85? 180hz to 440hz negative 16 so-16 (150 mils) ds3992z-09p+t&r -40? to +85? 90hz to 220hz positive 16 so-16 (150 mils) ds3992z-09n+t&r -40? to +85? 90hz to 220hz negative 16 so-16 (150 mils) DS3992Z-18P+t&r -40? to +85? 180hz to 440hz positive 16 so-16 (150 mils) ds3992z-18n+t&r -40? to +85? 180hz to 440hz negative 16 so-16 (150 mils) typical operating circuits appear at end of data sheet.
ds3992 two-channel, push-pull ccfl controller 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage on v cc relative to ground.......................-0.5v to +6.0v voltage on any leads other than v cc ..............0.5v to (v cc + 0.5v), not to exceed +6.0v operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +125? soldering temperature...................see j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.5 5.5 v svm voltage range v svm -0.3 v cc + 0.3 v bright voltage range v bright -0.3 v cc + 0.3 v lcm voltage range v lcm (note 2) -0.3 v cc + 0.3 v ovd voltage range v ovd (note 2) -0.3 v cc + 0.3 v gate-driver output charge loading q g 20 nc electrical characteristics (v cc = +4.5v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units supply current i cc g a , g b loaded with 600pf, 2 channels active 816ma low-level output voltage (ga, gb) v ol i ol = 4ma 0.4 v high-level output voltage (ga, gb) v oh1 i oh1 = -1ma v cc - 0.4 v uvlo threshold: v cc rising v uvlor 4.3 v uvlo threshold: v cc falling v uvlof 3.7 v uvlo hysteresis v uvloh 100 mv svm falling-edge threshold v svm 1.9 2.0 2.1 v svm hysteresis v svmh 150 mv lcm and ovd dc bias voltage v dcb 1.35 v lcm and ovd input resistance r dcb 50 k lamp-off threshold v lot (note 3) 1.65 1.75 1.85 v lamp over current v loc (note 3) 3.15 3.35 3.55 v lamp regulation threshold v lrt (note 3) 2.25 2.35 2.45 v ovd threshold v ovdt (note 3) 2.25 2.35 2.45 v lamp frequency range f lfs:osc 40 80 khz
ds3992 two-channel, push-pull ccfl controller _____________________________________________________________________ 3 note 1: all voltages are referenced to ground unless otherwise noted. currents into the i.c. are positive, out of the i.c. negative. note 2: during fault conditions, the ac-coupled feedback values are allowed to be below the absolute maximum rating of the lcm or ovd pin for up to 1s. note 3: voltage with respect to v dcb. electrical characteristics (continued) (v cc = +4.5v to +5.5v, t a = -40? to +85?.) parameter symbol conditions min typ max units lamp frequency tolerance f lfs:tol losc resistor ?% over temperature -10 +10 % ds3992z-09p/n 90 220 dpwm frequency range f dsr:osc DS3992Z-18P/n 180 440 hz dpwm frequency tolerance f dsr:tol posc resistor ?% over temperature -10 +10 % ds3992z-09p / DS3992Z-18P 0.5 bright voltage: minimum brightness v bmin ds3992z-09n / ds3992z-18n 2.0 v ds3992z-09p / DS3992Z-18P 2.0 bright voltage: maximum brightness v bmax ds3992z-09n / ds3992z-18n 0.5 v gate-driver output rise/fall time t r / t f c l = 600pf 50 100 ns gan and gbn duty cycle 44 % strike time t strike 500 ms typical operating characteristics (v cc = 5.0v, t a = +25?, unless otherwise noted.) 4.0 5.0 4.5 6.0 5.5 7.0 6.5 7.5 8.5 8.0 9.0 4.5 4.7 4.8 4.9 4.6 5.0 5.1 5.2 5.4 5.3 5.5 active supply current vs. supply voltage ds3992 toc01 supply voltage (v) supply current (ma) dpwm = 10% dpwm = 50% dpwm = 100% svm 2v gate q c = 3.5nc f lfosc = 64khz 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 -40.0 22.5 85.0 active supply current vs. temperature ds3992 toc02 temperature ( c) supply current (ma) v cc = 5.5v gate q c = 3.5nc f lfosc = 64khz dpwm = 100% v cc = 5.0v v cc = 4.5v -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 -40.0 22.5 85.0 internal frequency change vs. temperature ds3992 toc03 temperature ( c) frequency change (%) dpwm frequency lamp frequency
ds3992 two-channel, push-pull ccfl controller 4 _____________________________________________________________________ typical operating characteristics (continued) (v cc = 5.0v, t a = +25?, unless otherwise noted.) typical operation at 16v ds3992 toc04 10 s 5.0v g a 10 s 5.0v g b 10 s 2.0v lcm 10 s 2.0v ovd burst dimming at 150hz and 10% ds3992 toc05 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd typical startup with svm ds3992 toc06 2ms 2.0v svm 2ms 5.0v g b 2ms 2.0v lcm 2ms 2.0v ovd burst dimming at 150hz and 50% ds3992 toc07 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd soft-start at v inv = 16v ds3984 toc08 50 s 5.0v g a 50 s 5.0v g b 50 s 2.0v lcm 50 s 2.0v ovd lamp strike?xpanded view ds3992 toc09 1ms 5.0v g a 1ms 5.0v g b 1ms 2.0v lcm 1ms 2.0v ovd lamp out (lamp opened), autoretry disabled ds3992 toc10 0.25 5.0v g a 0.25 5.0v g b 0.25 2.00v lcm 0.25 2.00v ovd lamp opened
ds3992 two-channel, push-pull ccfl controller _____________________________________________________________________ 5 pin description pin number name i/o function 1 losc ? lamp oscillator resistor adjust. a resistor (r losc ) to ground on this pin sets the frequency of the lamp oscillator (f lfs:osc ). [r losc x f lfs:osc = 1.6e9]. 2 posc burst dimming dpwm oscillator resistor adjust. a resistor (rposc) to ground on this lead sets the frequency (f dsr:osc ) of the burst-dimming dpwm oscillator. [r posc x f dsr:osc = 4.0e6 for ds3992z-09p and ds3992z-09n and r posc x f dsr:osc = 8.0e6 for DS3992Z-18P and ds3992z-18n]. 3 bright i lamp brightness control. an analog voltage at this input controls the lamp brightness. see table 1 for details. 4 svm i supply voltage monitor. the dc inverter supply voltage is monitored by an external resistor divider. the resistor-divider should be set such that it provides 2v at this pin for the minimum allowable range of the dc inverter supply. pulling this input below 2v will turn the lamps off and reset the controller. connect to v cc if not used. 5 ga1 o mosfet gate drive a for channel 1. connect directly to the gate of a logic-level mode n-channel mosfet. 6 gb1 o mosfet gate drive b for channel 1. connect directly to the gate of a logic-level mode n-channel mosfet. 7 lcm1 i lamp current monitor input for channel 1. lamp current is monitored by a resistor placed in series with the low-voltage side of the lamp. 8 ovd1 i over voltage detection for channel 1. lamp voltage is monitored by a capacitor divider placed on the high-voltage side of the lamp. 9 gnd ? signal ground 10 v cc supply. 4.5v to 5.5v. 11 ga2 o mosfet gate drive a for channel 2. connect directly to the gate of a logic-level mode n-channel mosfet. 12 gb2 o mosfet gate drive b for channel 2. connect directly to the gate of a logic-level mode n-channel mosfet. 13 lcm2 i lamp current monitor input for channel 2. lamp current is monitored by a resistor placed in series with the low-voltage side of the lamp. 14 ovd2 i overvoltage detection for channel 2. lamp voltage is monitored by a capacitor divider placed on the high-voltage side of the lamp. 15 v cc ? supply. 4.5v to 5.5v. 16 v cc supply. 4.5v to 5.5v.
ds3992 two-channel, push-pull ccfl controller 6 _____________________________________________________________________ gan gbn ovdn overvoltage detection lcmn lamp current monitor [20.48mhz to 40.96mhz] 90hz to 220hz or 180hz to 440hz external resistor lamp frequency set v cc [4.5v to 5.5v] gnd two independent ccfl controllers (see figure 2) external resistor dpwm frequency set analog brightness control svm supply voltage monitor [40khz to 80khz] channel fault channel enable mosfet gate drivers losc bright posc dpwm signal 2.0v 40khz to 80khz oscillator ( 10%) 90hz to 220hz or 180hz to 440hz oscillator ( 10%) ramp generator x512 pll fault handling system enable / por vref uvlo ds3992 functional diagrams figure 1. ds3992 functional diagram
detailed description each ds3992 channel drives two logic-level n-channel mosfets that are connected between the ends of a step-up transformer and ground (see the typical operating circuits ). the transformer has a center tap on the primary side that is connected to the dc inverter voltage supply. the ds3992 alternately turns on the two mosfets to create the high-voltage ac waveform on the secondary side. by varying the duration of the mosfet turn-on times, the ds3992 is able to accurate- ly control the ccfl current. a resistor in series with the ccfl? ground connection enables current monitoring. the voltage across this resistor is fed to the lamp current monitor (lcm) input and compared to an internal reference voltage to deter- mine the duty cycle for the mosfet gates. the ds3992 supports a 1 lamp per channel configura- tion with fully independent lamp control and minimal external components. the ds3992 is also capable of controlling more than 1 lamp per channel using a wired-or feedback circuit. see the typical operating circuits section for more information. block diagrams of the ds3992 are shown in figures 1 and 2. more operating details of the ds3992 are dis- cussed on the following pages of this data sheet. dimming control the ds3992 uses ?urst?dimming to control the lamp brightness. an analog voltage applied at the bright input pin determines the duty cycle of a digital pulse- width-modulated (dpwm) signal (90hz to 220hz for ds3992z-09p/ds3992z-09n and 180hz to 440hz for DS3992Z-18P/ds3992z-18n). during the high period of the dpwm cycle, the lamp is driven at the selected lamp frequency (40khz to 80khz) as shown in figure 3. this part of the cycle is also called the ?urst?period because of the lamp frequency burst that occurs ds3992 two-channel, push-pull ccfl controller _____________________________________________________________________ 7 functional diagrams (continued) gate drivers gan gbn digital ccfl controller channel fault 512 x lamp frequency [20.48mhz to 40.96mhz] lamp frequency [40khz to 80khz] dimming pwm signal channel enable mosfet gate drivers lcmn lamp current monitor 400mv 2.0v lamp overcurrent lamp strike and regulation lamp out 1.0v 1.0v ovdn overvoltage detector lamp maximum voltage regulation 64 lamp cycle integrator overvoltage figure 2. ds3992 per channel logic diagram 90hz to 220hz or 180hz to 440hz lamp current dpwm signal figure 3. digital-pwm dimming and soft-start
ds3992 during this time. during the low period of the dpwm cycle, the controller disables the mosfet gate drivers so the lamp is not driven. this causes the current to stop flowing in the lamp, but the time is short enough to keep the lamp from de-ionizing. dimming is increased/ decreased by adjusting (i.e., modulating) the burst period duty cycle. at the beginning of each burst dim- ming cycle, there is a soft-start whereby the lamp cur- rent is slowly ramped to reduce the potential to create audible transformer noise. the slope of the bright dimming input is either posi- tive or negative as shown in table 1. for voltages between 0.5v and 2.0v, the duty cycle will vary linearly between the minimum and 100%. lamp strike on lamp strike, the ds3992 boosts the normal operat- ing lamp frequency by 33%. this is done to increase the voltage created and help insure that the lamp strikes. in addition, the maximum strike voltage will be applied to the lamp for over 500ms. once the controller detects that the lamp has struck, the frequency is returned to the normal lamp frequency. setting the lamp and dpwm frequencies using external resistors both the lamp and dpwm frequencies are set using external resistors. the resistance required for either fre- quency can be determined using the following formula: where k = 1600k x khz for lamp frequency calcula- tions. when calculating the resistor value for the dpwm frequency, k will be one of two values depending on the ds3992 version. if using the -09n/p version (90hz to 220hz) then k = 4k x khz. k = 8k x khz for the -18n/p version (180hz to 440hz). example: selecting the resistor values to configure the -09p version to have a 50khz lamp frequency and a 160hz dpwm frequency: for the dpwm resistor calcula- tion, k = 4k x khz. for the lamp-frequency-resistor (r losc ) calculation, k = 1600k x khz, which is always the lamp frequency k value regardless of the frequency. the previous formula can now be used to calculate the resistor values for r losc and r posc as follows: supply monitoring the ds3992 has supply voltage monitors for both the inverter? dc supply (v inv ) and its own v cc supply to ensure that both voltage levels are adequate for proper operation. the inverter supply is monitored for under- voltage conditions at the svm pin. an external resistor- divider at the svm input feeds into a comparator (see figure 1) having a 2v threshold. using the equation below to determine the resistor values, the inverter sup- ply trip point (v trip ) can be customized to shut off the inverter when the inverter supply voltage drops below the specified value. operating with the inverter voltage at too high of a level can be damaging to the inverter components. proper use of the svm can prevent this problem. if desired, svm can be disabled by connecting the svm pin to gnd. the v cc monitor is a 5v supply undervoltage lockout (uvlo) that prevents operation when the ds3992 does not have adequate voltage for its analog circuitry to operate or to drive the external mosfets. the v cc monitor features hysteresis to prevent v cc noise from causing spurious operation when v cc is near the trip point. this monitor cannot be disabled by any means. fault monitoring the ds3992 provides extensive fault monitoring for each channel. it can detect open-lamp, lamp overcur- rent, failure to strike, and overvoltage conditions. figure 4 shows a flowchart of how the ds3992 controls and monitors each channel. the steps are as follows: the lamps will not turn on unless the ds3992 supply voltage is > 4.5v and the voltage at the supply voltage monitor (svm) input is > 2v. v rr r trip . = + ? ? ? ? ? ? 20 12 1 r k x khz khz k r k x khz khz k losc posc . == == 1600 50 32 4 0 160 25 r f osc = k osc two-channel, push-pull ccfl controller 8 _____________________________________________________________________ table 1. bright analog dimming input configuration device slope minimum brightness maximum brightness ds3992z-09p and DS3992Z-18P positive bright < 0.5v bright > 2.0v ds3992z-09n and ds3992z-18n negative bright > 2.0v bright < 0.5v
ds3992 two-channel, push-pull ccfl controller _____________________________________________________________________ 9 when both the ds3992 and the dc inverter supplies are at acceptable levels, the ds3992 will attempt to strike the lamps. the ds3992 slowly ramps up the mosfet gate duty cycle until the lamp strikes. the controller detects that the lamp has struck by detecting current flow in the lamp. if during the strike ramp, the maximum allowable voltage is reached, the controller will stop increasing the mosfet gate duty cycle to keep from overstressing the system. the ds3992 will go into a fault-handling state if the lamp has not struck after 65,536 lamp cycles. if an overvoltage event is detected during the strike attempt, the ds3992 will dis- able the mosfet gate drivers and go into the fault- handling state. once the lamp is struck, the ds3992 moves to the run lamp stage. in the run lamp stage, the ds3992 adjusts the mosfet gate duty cycle to optimize the lamp cur- rent. the gate duty cycle is always constrained to keep the system from exceeding the maximum allowable lamp voltage. if lamp current ever drops below the lamp out reference point for 65536 lamp cycles, then the lamp is considered extinguished. in this case the mosfet gate drivers are disabled and the device moves to the fault handling stage. in the case of a lamp overcurrent condition, the ds3992 will instantaneously declare the controller to be in a fault state. if either channel on the ds3992 goes into the fault state, only the faulty channel will be shut down. once a fault state is entered, the controller will remain in that state until one of the following occurs: ? cc drops below the uvlo threshold. the svm input drops below 2.0v. applications information component selection external component selection has a large impact on the overall system performance and cost. the two most important external components are the transformers and n-channel mosfets. the transformer should be able to operate in the 40khz to 80khz frequency range of the ds3992, and the turns ratio should be selected so the mosfet drivers run at 28% to 35% duty cycle during steady-state operation. the transformer must be able to withstand the high open-circuit voltage that will be used to strike the lamp. additionally, its primary/secondary resistance and inductance characteristics must be considered because they contribute significantly to determining the yes mosfet gate drivers enabled run lamp stage device and inverter supplies at proper levels? fault state [must power cycle the ds3992 or take svm below 2v to reset the ccfl controller] lamp overcurrent [instantaneous] strike lamp [ramp and regulate to ovd threshold] lamp strike timeout [65536 lamp cycles] run lamp [regulate lamp current bounded by lamp voltage] lamp-out timeout [65,536 lamp cycles] overvoltage [64 lamp cycles] if line regulation threshold is met figure 4. fault-handling flowchart
ds3992 efficiency and transient response of the system. table 2 shows a transformer specification that has been utilized for a 12v inverter supply, 438mm x 2.2mm lamp design. the n-channel mosfet must have a threshold voltage that is low enough to work with logic-level signals, a low on-resistance to maximize efficiency and limit the n- channel mosfet? power dissipation, and a break- down voltage high enough to handle the transient. the breakdown voltage should be a minimum of 3x the inverter voltage supply. additionally, the total gate charge must be less than q g , which is specified in the recommended operating conditions table. these specifications are easily met by many of the dual n- channel mosfets now available in so-8 packages. two-channel, push-pull ccfl controller 10 ____________________________________________________________________ table 2. transformer specifications (as used in the typical operating circuit ) parameter conditions min typ max units turns ratio (secondary/primary) (notes 1, 2, 3) 40 frequency 40 80 khz output power 6w output current 58ma primary dcr center tap to one end 200 m secondary dcr 500 primary leakage 12 ? secondary leakage 185 mh primary inductance 70 ? secondary inductance 500 mh 1000ms minimum 2000 secondary output voltage continuous 1000 v rms note 1: primary should be bifilar wound with center tap connection. note 2: turns ratio is defined as secondary winding divided by the sum of both primary windings. note 3: 40:1 is the nominal turns ratio for driving a 438mm x 2.2mm lamp with a 12v supply. refer to an3375 for more information.
ds3992 two-channel, push-pull ccfl controller ____________________________________________________________________ 11 inverter supply voltage (5v 10% to 24v 10%) gb1 ovd1 lcm1 svm ga1 ccfl lamp dual power mosfet r lcm transformer overvoltage detection lamp current monitor v cc device supply voltage (5v 10%) v cc v cc bright analog lamp brightness control losc posc resistor set lamp frequency resistor set burst dimming frequency gb2 ovd2 lcm2 gnd ga2 ccfl lamp dual power mosfet r lcm transformer overvoltage detection lamp current monitor ds3992 r lcm i lamp(rms 2 1 x typical operating circuits single per channel operating circuit
ds3992 two-channel, push-pull ccfl controller 12 ____________________________________________________________________ inverter supply voltage (12v 10% to 24v 10%) on = open off/reset = closed gb ovd lcm svm ga ccfl lamp a ccfl lamp b ccfl lamp c dual n-channel power mosfet 2n3904 +5v 1 of 2 channels v cc device supply voltage (5v 10%) v cc v cc bright analog lamp brightness control losc posc resistor set lamp frequency resistor set burst dimming frequency gnd ds3992 2n3904 +5v 2n3904 +5v typical operating circuits (continued) multi-lamp per channel operating circuit
ds3992 two-channel, push-pull ccfl controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. springer power-supply decoupling to achieve best results, it is highly recommended that a decoupling capacitor be used on pin 10, the ic power- supply pin. pins 15 and 16, also v cc pins, do require connection to supply voltage, but do not require any additional decoupling. typical values of decoupling capacitors are 0.01? or 0.1?. use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the v cc and gnd pins of the ic to minimize lead inductance. chip topology transistor count: 53,000 substrate connected to ground package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .

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